The present invention relates to a system for and a method of producing a design for and manufacturing a semiconductor device. The present invention also relates to a semiconductor device manufactured by such a system or method, to a computer program for controlling a computer forming such a system, and to a medium containing such a computer program.
There is a requirement for rapid design and production of semiconductor devices such as integrated circuits which work correctly and meet their desired performance parameters xe2x80x9cfirst timexe2x80x9d, in other words without requiring extensive redesign or different stages of prototyping. For example, this is required of mixer-oscillator products for use in tuners having low noise figures and high intermodulation distortion performance (IIP3). Known techniques for achieving this rely on the reuse and optimization of previously designed circuit cells for discrete circuit blocks. However, this optimization procedure is very time consuming and requires an extensive understanding of the limitations of previously used circuits.
According to a first aspect of the invention, there is provided a system for producing a design for and/or manufacturing a semiconductor device. This aspect includes a first library of at least one template, the or each of which comprises a representation of a discrete circuit block and at least one equation relating at least one performance parameter of the circuit block to at least one electrical parameter of at least one component of the circuit block. A first selecting means is operative for selecting the template or one of the templates from the library. A second selecting means is operative for selecting a desired value of the at least one performance parameter of the circuit block of the selected template. A calculating means is operative for calculating a value of the at least one electrical parameter for achieving the desired value of the at least one performance parameter by entering the desired value of the at least one performance parameter in the at least one equation and solving the at least one equation for the at least one electrical parameter so as to form a design of the semiconductor device. The design is used and acted upon to manufacture the semiconductor device.
The at least one electrical parameter may comprise a component value of the at least one component. The at least one component may comprise at least one resistive component and the component value may comprise the resistance thereof.
The at least one performance parameter may comprise a noise figure.
The at least one performance parameter may comprise a distortion value.
The first selecting means may comprise first manual selection means.
The at least one equation may comprise a plurality of simultaneous equations. The at least one performance parameter may comprise a plurality of performance parameters. The at least one electrical parameter may comprise a plurality of electrical parameters. The at least one component may comprise a plurality of components.
The calculating means may calculate a plurality of values of the at least one component, the system comprising third selecting means for selecting one of the calculated values in accordance with a predetermined criterion. The predetermined criterion may be lowest power dissipation. The system may comprise a second library of manufacturing process files, each of which comprises predetermined electrical parameters of at least one type of component of the circuit blocks. The at least one type of component may comprise a transistor. The system may comprise fourth selecting means for selecting a process file from the second library. The fourth selecting means may comprise second manual selection means. The calculating means may enter at least some of the predetermined electrical parameters of the selected process file in the at least one equation in order to calculate the value of the at least one electrical parameter. The calculating means may be arranged to calculate the size of the at least one component, such as at least one resistor in accordance with the current which it is required to pass.
The system may comprise means for producing a schematic of the circuit block of the selected template including the calculated value of the at least one electrical parameter of the at least one component. The system may comprise means for simulating the operation of the schematic including calculating a simulated value of the at least one performance parameter. The semiconductor device may comprise at least part of an integrated circuit.
The circuit block of the at least one template may comprise a long tail pair of bipolar transistors for radio frequency use, the at least one performance parameter may comprise a noise figure NF and a third order intermodulation distortion d3, the at least one electrical parameter may comprise load resistance R1, emitter degeneration resistance Re and internal emitter resistance re of the long tail pair of transistors, and the at least one equation may comprise:             N      ⁢              xe2x80x83            ⁢      F        =          10      ⁢              xe2x80x83            ⁢                        log          10                [                                                                              R                  ⁢                                      xe2x80x83                                    ⁢                  s                                +                                                      R                    ⁢                                          xe2x80x83                                        ⁢                                          s                      2                                                                            R                    ⁢                                          xe2x80x83                                        ⁢                    f                                                  +                                                      [                                                                                            R                          ⁢                                                      xe2x80x83                                                    ⁢                          s                                                +                                                  R                          ⁢                                                      xe2x80x83                                                    ⁢                          f                                                                                            R                        ⁢                                                  xe2x80x83                                                ⁢                        f                                                              ]                                    2                                                            R                ⁢                                  xe2x80x83                                ⁢                s                                      ·            R                    ⁢                      xe2x80x83                    ⁢          a          ⁢                      xe2x80x83                    ⁢          m          ⁢                      xe2x80x83                    ⁢          p                ⁢                  xe2x80x83                ]                        R      ⁢              xe2x80x83            ⁢      a      ⁢              xe2x80x83            ⁢      m      ⁢              xe2x80x83            ⁢      p        ⁢          xe2x80x83        =                  2        ⁢        R        ⁢                  xe2x80x83                ⁢        e            +              2        ⁢        r        ⁢                  xe2x80x83                ⁢        b        ⁢                  xe2x80x83                ⁢        b            +                                    2            ⁡                          [                                                R                  ⁢                                      xe2x80x83                                    ⁢                  e                                +                                  r                  ⁢                                      xe2x80x83                                    ⁢                  e                                +                                  [                                                                                    r                        ⁢                                                  xe2x80x83                                                ⁢                        b                        ⁢                                                  xe2x80x83                                                ⁢                        b                                            +                                              R                        ⁢                                                  xe2x80x83                                                ⁢                        s                                                              β                                    ]                                            ]                                2                          R          ⁢                      xe2x80x83                    ⁢          l                    +              r        ⁢                  xe2x80x83                ⁢        e            +                        1                      2            ⁢                          β              ·              r                        ⁢                          xe2x80x83                        ⁢            e                          ⁢                              (                                          R                ⁢                                  xe2x80x83                                ⁢                e                            +                              R                ⁢                                  xe2x80x83                                ⁢                s                            +                              r                ⁢                                  xe2x80x83                                ⁢                b                ⁢                                  xe2x80x83                                ⁢                b                                      )                    2                    +                        1                      2            ⁢                          β              ·              r                        ⁢                          xe2x80x83                        ⁢            e                          ⁢                              (                                          R                ⁢                                  xe2x80x83                                ⁢                e                            +                              r                ⁢                                  xe2x80x83                                ⁢                b                ⁢                                  xe2x80x83                                ⁢                b                                      )                    2                          d3    =                            (                                    v              ⁢                              xe2x80x83                            ⁢              i              ⁢                              xe2x80x83                            ⁢              n                                      V              ⁢                              xe2x80x83                            ⁢              t                                )                2                              48          ⁡                      [                          1              +                                                R                  ⁢                                      xe2x80x83                                    ⁢                  e                                                  r                  ⁢                                      xe2x80x83                                    ⁢                  e                                                      ]                          3            
where
Rs is the source resistance to which the long tail pair is to be connected;
Rf is a feedback resistance of the long tail pair;
rbb is the base spreading resistance of the bipolar transistors;
xcex2 is the current gain of the bipolar transistors;
re=50 mV/Iee; and
Iee is the emitter current of the bipolar transistors.
The system may comprise a computer programmed by a computer program.
According to a second aspect of the invention, there is provided a method of producing a design for and/or manufacturing a semiconductor device. This aspect includes the steps of selecting from a library a template comprising a representation of a discrete circuit block and at least one equation relating at least one performance parameter of the circuit block to at least one electrical parameter of at least one component of the circuit block; selecting a desired value of the at least one performance parameter of the circuit block; calculating a value of the at least one electrical parameter for achieving the desired value of the at least one performance parameter by entering the desired value of the at least one performance parameter in the at least one equation; and solving the at least one equation for the at least one electrical parameter so as to form a design of the semiconductor device; and using and acting on the design to manufacture the semiconductor device.
According to a third aspect of the invention, there is provided a semiconductor device manufactured by a system according to the first aspect of the invention or by a method according to the second aspect of the invention.
According to a fourth aspect of the invention, there is provided a computer program for a computer for constituting the system according to the first aspect of the invention.
According to a fifth aspect of the invention, there is provided a medium containing a computer program according to the third aspect of the invention.
It is thus possible to provide a system which is able to optimize one or more different types of discrete circuit blocks from a library of such blocks. In particular, it is possible to produce a semiconductor device, which may be part of an integrated circuit, which meets one or more performance parameters essentially merely by specifying the desired values of such parameters. It has been found that values of components of such circuit blocks can be derived from the required performance parameters and the resulting designs when produced can achieve the required performance parameters with a very high probability. This probability can be increased by automatically simulating the resulting designs and this allows checking of whether the desired performance parameters can be met, for example over a range of temperatures and supply voltages. Thus, the extensive optimization procedures and prototyping steps of known techniques can be substantially avoided or at least greatly reduced. Thus, productivity can be increased without compromising design integrity.
The novel features which are considered as characteristic of the invention are set forth in particular in the appended claims. The invention itself, however, both as to its construction and its method of operation, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.